Combinational Circuit MCQ : 


Q1.  Logic depends only on present value of input is
combinational logic
sequential logic
systematic logic
correctional logic
Ans:-A
Q2.  Which sequential circuits generate the feedback path due to the cross-coupled connection from output of one gate to the input of another gate?
a.Synchronous
b. Asynchronous
c. Both
d. None of the above
Ans:-b
Q3. What is/are the crucial function/s of memory elements used in the sequential circuits?
a.Storage of binary information
b. Specify the state of sequential 
c. Both a & b
d. None of the above
Ans:-c
Q4.A The behaviour of synchronous sequential circuit can be predicted by defining the signals at ______.

a. discrete instants of time
b. continuous instants of time
c. sampling instants of time 
d. at any instant of time
Ans:a
Q5.  Which memory elements are utilized in an asynchronous & clocked sequential circuits respectively?
Time- delay devices & registers
b. Time- delay devices & flip-flops
c. Time- delay devices & counters
d. Time-delay devices & latches
Ans:-b
Q6. Why do the D-flipflops receives its designation or nomenclature as 'Data Flipflops' ?

a. Due to its capability to receive data from fliflop
b. Due to its capability to store data in flipflop
c. Due to its capability to transfer the data into flipflop
d. All of the above
Ans:-c
Q7. The characteristic equation of D-flipflop implies that _____.
the next state is dependent on previous state
b. the next state is dependent on present state
c. the next state is independent of previous state
d. the next state is independent of present state
Ans:-d
Q8. Which circuit is generated from D-flipflop due to addition of an inverter by causing reduction in the number of inputs?
Gated JK- latch
b. Gated SR- latch
c. Gated T- latch
d. Gated D- latch 
Ans:-d
Q9. What is the bit storage binary information capacity of any flipflop?

a. 1 bit
b. 2 bits
c. 16 bits
d. infinite bits
Ans:a

Q10. What is/are the directional mode/s of shifting the binary information in a shift register?

a. Up-Down
b. Left - Right
c. Front - Back
d. All of the above
Ans:-B


Q11. Which time interval specify the shifting of overall contents of the shift registers?

a. Bit time
b. Shift time
c. Word time
d. Code time
Ans;-C
Q12. Which type of shift register is renowned as 'bit bucket brigade circuit' by presenting the input data and applying the clock pulse for the movement of bits across the storage elements?

a. Serial In - Serial Out (SISO)
b. Serial In - Parallel Out (SIPO)
c. Parallel In - Parallel Out (PIPO)
d. Parallel In - Serial Out (PISO)

ANSWER: a. Serial In -Serial Out (SISO)


Q13. What is the value of a time delay introduced in the system of digital delay line shift register especially on the appearance of an input pulse train?

a. ( n + 1 ) T = Δ
b. ( n - 1 ) T = Δ
c. ( n + 1 ) / T = Δ
d. ( n - 1 ) / T = Δ

ANSWER: b. (n -1 ) T = Δ

Q14. Which kind of dynamic shift register has a provision of repeating the code continuously by connecting its output back to the serial input?

a. PIPO Register
b. SISO Register
c. Multi-mode Shift Register
d. Reintrant Shift Register

ANSWER: d. Reintrant Shift Register

Q15. A counter is fundamentally a _________ sequential circuit that proceeds through the predetermined sequence of states only when input pulses are applied to it.

a. register
b. memory unit
c. flipflop
d. arithmatic logic unit



ANSWER: a. register


Q16.Match the following sequential Circuits with associated functions 

1. Counter -------- A. Storage of Program & data in a digital computer

2. Register -------- B. Generation of timing variables to sequence the digital system operations 

3. Memory --------- C. Design of Sequential Circuits

Codes:

a. 1-A , 2-B , 3-C
b. 1-C , 2-B , 3-A
c. 1-C , 2-A , 3-B
d. 1-B , 2-C , 3-A 

ANSWER: d. 1-B , 2-C , 3-A

Q17. What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of 'n' number of flipflops?

a. 0 to 2n
b. 0 to 2n-1
c. 0 to 2n+1
d. 0 to 2n+1 / 2 

ANSWER: b. 0 to 2n-1

Q18. Which property of unit distance counters has the potential to overcome the consequences of multi-bit change flashing that arises in almost all conventional binary and decimal counters?

a. one bit change per unit change
b. two bits change per unit change
c. three bits change per unit change
d. four bits change per unit change
ANSWER: a. one bit change per unit change


Q19. What contributes to the triggering of clock pulse inputs for all the flipflops excluding the first flipflop in a ripple counter?

a. Incoming Pulses
b. Output Transistion
c. Double Clock Pulses
d. All of the above

 

ANSWER: b. Output Transistion


Q20. What is the required relationship between number of flipflops and the timing signals in Johnson Counter?

a. No. of flipflops = 1/2 x No. of timing signals
b. No. of flipflops = 2/3 x No. of timings signals
c. No. of flipflops = 3/4 x No. of timing signals
d. No. of flipflops = 4 x No. of timing signals 

ANSWER: a. No. of flipflops = 1/2 x No. of timing signals

1. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
a)Lowinput voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling

Answer: d
Explanation: Both inputs of a latch are directly connected to the other’s output. Such types of structure is called cross coupling and due to which latches remain in the latched condition.
2. One example of the use of an S-R flip-flop is as:
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator

Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce.
3. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4

Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state.
4. When both inputs of a J-K flip-flop cycle, the output will
a) Be invalid
b) Change
c) Not change
d) Toggle

Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete).
5. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH

Answer: a
Explanation: In D flip flop, when the clock is high then the out depends on the input otherwise reminds previous output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then output is also zero.
6. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates

7. The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops

Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called sequential circuits.
8. Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops

Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since, the combinational circuits do not require memory elements whereas the sequential circuits need memory devices to perform their operations in sequence.
9. How many types of sequential circuits are?
a) 2
b) 3
c) 4
d) 5

Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked.
10. The sequential circuit is also called
a) Flip-flop
b) Latch
c) Strobe
d) None of the Mentioned

Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit of information.
11. The basic latch consist of
a) Two inverters
b) Two comparators
c) Two amplifiers
d) None of the Mentioned

Answer: a
Explanation: The basic latch consist of two inverters. It is in the sense that if the output Q = 0 then the second output Q’ = 1 and vice versa.
12. If Q = 0, the output is said to be
a) Set
b) Reset
c) Previous state
d) Current state

Answer: a
Explanation: If Q = 0, the output is said to be set and reset for Q’ = 1.





1. 
Convert hexadecimal value 16 to decimal.


A.
2210

B.
1610

C.
1010

D.
2010

Answer: Option A