Multiple Choice Questions
Unit 1:-Digital Circuit

1.In boolean algebra, the OR operation is performed by which properties?
a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned
Answer: d
Explanation: The expression for Associative property is given by A+(B+C) = (A+B)+C & A*(B*C) = (A*B)*C.
The expression for Commutative property is given by A+B = B+A & A*B = B*A.
The expression for Distributive property is given by A+BC=(A+B)(A+C) & A(B+C) = AB+AC.

2.The expression for Absorption law is given by
a) A+AB = A
b) A+AB = B
c) AB+AA’ = A
d) None of the Mentioned
Answer: a
Explanation: The expression for absorption law is given by – A+AB = A.

3. According to boolean law: A + 1 = ?
a) 1
b) A
c) 0
d) A’
Answer: a
Explanation: A + 1 = A.

4. The involution of A is equal to
a) A
b) A’
c) 1
d) 0
Answer: a
Explanation: The involution of A means double inversion of A(i.e. A”) and is equal to A.

5.A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A
Answer: d
Explanation: A(A + B) = AA + AB = A + AB = A(1 + B) = A*1 = A.

6.DeMorgan’s theorem states that
a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) None of the Mentioned
Answer: a
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’.

7.(A + B)(A’ * B’) = ?
a) 1
b) 0
c) AB
d) AB’
Answer: b
Explanation: (A + B)(A’ * B’) = AA’B’ + BA’B’ = 0 + BB’A’ = 0 + 0 = 0 (AA’ = BB’ = 0).

8.Complement of the expression A’B + CD’ is
a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
Answer: b
Explanation: (A’B + CD’)’ = (A’B)'(CD’)’ = (A” + B’)(C’ + D”) = (A + B’)(C’ + D).

9.Simplify Y = AB’ + (A’ + B)C
a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A
Answer: a
Explanation: Y = AB’ + (A’ + B)C = AB’ + (A’ + B)C = AB’ + (AB’)’C = AB’ + C.

10.The boolean function A + BC is a reduced form of
a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B
Answer: b
Explanation: (A + B)(A + C) = AA + AC + AB + BC = A + AC + AB + BC = A(1 + C + B) + BC = A + BC.

11.The logical sum of two or more logical product terms is called
a) SOP
b) POS
c) OR operation
d) NAND operation
Answer: a
Explanation: The logical sum of two or more logical product terms, is called SOP (i.e. sum of product).

12.The expression Y=AB+BC+AC shows the _________ operation.
a) EX-OR
b) SOP
c) POS
d) NOR
Answer: b
Explanation: The given expression has the operation product as well as the sum of that. So, it shows SOP operation.

13.The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.
a) AND
b) POS
c) SOP
d) NAND
Answer: b
Explanation: The given expression has the operation sum as well as the product of that. So, it shows POS(product of sum) operation.

14.A product term containing all K variables of the function in either complemented or uncomplemented form is called a
a) Minterm
b) Maxterm
c) Midterm
d) None of the Mentioned
Answer: a
Explanation: A product term containing all K variables of the function in either complemented or uncomplemented form is called a minterm.

15.According to the property of minterm, how many combination will have value equal to 1 for K input variables?
a) 0
b) 1
c) 2
d) 3
             Answer: b
           Explanation: The main property of a minterm is that it possesses the value 1 for only one combination of K input variables and the remaining will have the value 0. 

16.The canonical sum of product form of the function y(A,B) = A + B is
a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) None of the Mentioned
Answer: b
Explanation: A + B = A.1 + B.1 = A(B + B’) + B(A + A’) = AB + AB’ + BA +BA’ = AB + AB’ + A’B = AB + AB’ + A’B.

17.A variable on its own or in its complemented form is known as a
a) Product Term
b) Literal
c) Sum Term
d) None of the Mentioned
Answer: b
Explanation: A literal is a single logic variable or its complement. For example — X, Y, A’, Z, X’ etc.

18.Maxterm is the sum of __________of the corresponding Minterm with its literal complemented.
a) Terms
b) Words
c) Numbers
d) None of the Mentioned
Answer: a
Explanation: Maxterm is the sum of terms of the corresponding Minterm with its literal complemented.

19.Canonical form is a unique way of representing________________
a) SOP
b) Minterm
c) Boolean Expressions
d) A page
Answer: c
Explanation: Boolean Expressions are represented through canonical form. An example of canonical form is A’B’C’ + AB’C + ABC’.

20.There are _____________ Minterms for 3 variables (a, b, c).
a) 0
b) 2
c) 8
d) None of the Mentioned
Answer: c
Explanation: Minterm is given by 2^n. So, 2^3 = 8 minterms are required.

21._____________ expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-level NAND logic circuits.
a) POS
b) Literals
c) SOP
d) None of the Mentioned
Answer: c
Explanation: SOP expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-level NAND logic circuits.

22.A Karnaugh map (K-map) is an abstract form of ____________ diagram organized as a matrix of squares.
a) Venn Diagram
b) Cycle Diagram
c) Block diagram
d) Triangular Diagram
Answer: a
Explanation: A Karnaugh map (K-map) is an abstract form of Venn diagram organized as a matrix of squares.
There are ______ cells in a 4-variable K-map.
a) 12
b) 16
c) 18
d) None of the Mentioned
Answer: b
Explanation: There are 16(2^4) cells in a 4-variable K-map.

23.The K-map based Boolean reduction is based on the following Unifying Theorem: A + A’ = 1.
a) Impact
b) Non Impact
c) Force
d) None of the Mentioned
Answer: b
Explanation: The given expression A +A’ = 1 is based on non-impact unifying theorem.

24.Each product term of a group, w’.x.y’ and w.y, represents the ____________in that group.
a) Input
b) POS
c) Sum-of-Minterms
d) None of the Mentioned
Answer: c
Explanation: In a minterm, each variable w, x or y appears once either as the variable itself or as the inverse. So, the given expression satisfies the property of Sum of Minterm.

25.The prime implicant which has at least one element that is not present in any other implicant is known as
a) Essential Prime Implicant
b) Implicant
c) Complement
d) None of the Mentioned
Answer: a
Explanation: Essential prime implicants are prime implicants that cover an output of the function that no combination of other prime implicants is able to cover.

26.Product-of-Sums expressions can be implemented using
a) 2-level OR-AND logic circuits
b) 2-level NOR logic circuits
c) 2-level XOR logic circuits
d) Both 2-level OR-AND and NOR logic circuits
Answer: d
Explanation: Product-of-Sums expressions can be implemented using 2-level OR-AND & NOR logic circuits.

27.Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible product term of the given
a) Function
b) Value
c) Set
d) None of the Mentioned
Answer: a
Explanation: Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible product term of the given function.

28.Don’t care conditions can be used for simplifying Boolean expressions in
a) Examples
b) Terms
c) K-maps
d) Latches
Answer: c
Explanation: Don’t care conditions can be used for simplifying Boolean expressions in K-maps which helps in pairing with 1/0.

29.It should be kept in mind that don’t care terms should be used along with the terms that are present in
a) Minterms
b) Maxterm
c) K-Map
d) Latches
Answer: a
Explanation: It should be kept in mind that don’t care terms should be used along with the terms that are present in minterms which reduces the complexity of the boolean expression.

30.Using the transformation method you can realize any POS realization of OR-AND with only.
a) XOR
b) NAND
c) AND
d) NOR
Answer: d
Explanation: Using the transformation method we can realize any POS realization of OR-AND with only NOR.

31.There are many situations in logic design in which simplification of logic expression is possible in terms of XOR and _________________ operations.
a) X-NOR
b) XOR
c) NOR
d) NAND
Answer: a
Explanation: There are many situations in logic design in which simplification of logic expression is possible in terms of XOR and XNOR operations.

32.These logic gates are widely used in _______________ design and therefore are available in IC form.
a) Circuit
b) Digital
c) Analog
d) Block
Answer: b
Explanation: These logic gates(XOR,XNOR,NOR) are widely used in digital design and therefore are available in IC form.

33.In case of XOR/XNOR simplification we have to look for the following____________________
a) Diagonal Adjacencies
b) Offset Adjacencies
c) Straight Adjacencies
d) Both diagonal and offset adjencies
Answer: d
Explanation: In case of XOR/XNOR simplification we have to look for the following diagonal and offset adjacencies.

34.Entries known as _______________ mapping.
a) Diagonal
b) Straight
c) K
d) None of the Mentioned
Answer: a
Explanation: Entries known as diagonal mapping.

35. The output of an EX-NOR gate is 1. Which input combination is correct?
a) A = 1, B = 0
b) A = 0, B = 1
c) A = 0, B = 0
Answer: c
Explanation: The output of EX-NOR gate is given by (AB’ + A’B)’. So, for A = 0 and B = 0 the output will be 1.

36.In which of the following gates the output is 1 if and only if at least one input is 1?
a) AND
b) NOR
c) NAND
d) OR
Answer: d
Explanation: In or gate we need at least one bit to be equal to 1 to generate the output as 1 because OR means any of the condition out of two is equal to 1 which means if at least one input is 1 then it shows output as 1.

37.The time required for a gate or inverter to change its state is called
a) Rise time
b) Decay time
c) Propagation time
d) Charging time
Answer: c
Explanation: The time required for a gate or inverter to change its state is called propagation time.

38.What is the minimum number of two input NAND gates used to perform the function of two input OR gates?
a) One
b) Two
c) Three
d) Four
Answer: c
Explanation: Y = A + B. This is the equation of OR gate. We require 3 NAND gates to create OR gate. We can also write,
1st, 2nd and 3rd NAND operations as: Y = (A AND B)’ = A.B = (A.B)’.

Odd parity of word can be conveniently tested by
a) OR gate
b) AND gate
c) NAND gate
d) XOR gate
Answer: d
Explanation: Odd parity of word can be conveniently tested by XOR gate.

The number of full and half adders are required to add 16-bit number is
a) 8 half adders, 8 full adders
b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders
d) 4 half adders, 12 full adders
Answer: b
Explanation: One half adder can add the least significant bit of the two numbers whereas full adders are required to add the remaining 15 bits as they all involve adding carries.

Which of the following will give the sum of full adders as output?
a) Three point major circuit
b) Three bit parity checker
c) Three bit comparator
d) Three bit counter
Answer: d
Explanation: Three bit counter will give the sum of full adders as output.

Which of the following gate is known as coincidence detector?
a) AND gate
b) OR gate
c) NOR gate
d) NAND gate
Answer: a
Explanation: AND gate is known as coincidence detector due to multiplicity behaviour.

An OR gate can be imagined as
a) Switches connected in series
b) Switches connected in parallel
c) MOS transistor connected in series
d) None of the mentioned
Answer: b
Explanation: OR gate means addition of two inputs, due to this reason it is imagined as switches connected in parallel.

How many full adders are required to construct an m-bit parallel adder?
a) m/2
b) m
c) m-1
d) m+1
Answer: c
Explanation: We need adder for every bit. So we should need m bit adders. A full adder adds a carry bit to two inputs and produces an output and a carry. But the most significant bits can use a half adder which differs from the full adder as in that it has no carry input, so we need m-1 full adders in m bit parallel adder

The output of a logic gate is 1 when all the input are at logic 0 as shown below:
Input
Output

A
B
C

0
0
1

0
1
0

1
0
0




Input
Output

A
B
C

0
0
1

0
1
0

1
0
0


The gate is either
a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR
Answer: d
Explanation: The output of a logic gate is 1 when all inputs are at logic 0. The gate is either a NOR or an EX-NOR. (The truth tables for NOR and EX-NOR Gates are shown in above figure.)

48.The code where all successive numbers differ from their preceding number by single bit is
a) Binary code
b) BCD
c) Excess 3
d) Gray
Answer: d
Explanation: The code where all successive numbers differ from their preceding number by single bit is gray code. It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next.

49.The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
Answer: c
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.

50.How many AND gates are required to realize Y = CD + EF + G ?
a) 4
b) 5
c) 3
d) 2
Answer: d
Explanation: To realize Y = CD + EF + G, two AND gates are required.

51. The NOR gate output will be high if the two inputs are
a) 00
b) 01
c) 10
d) 11
Answer: a
Explanation: In option b, c or d output is low if any of the I/P is high. So, the correct option will be a.

52. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) None of the Mentioned
Answer: a
Explanation: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.

53. A universal logic gate is one which can be used to generate any logic function. Which of the following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND
Answer: d
Explanation: NAND can generate any logic function.

54. A full adder logic circuit will have
a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
Answer: d
Explanation: A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.

55. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
a) 1, 1
b) 4, 2
c) 3, 2
d) 2, 3
Answer: a
Explanation: There are three product terms. So, three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.

56. Which of following are known as universal gates?
a) NAND & NOR
b) AND & OR
c) XOR & OR
d) None of the Mentioned
Answer: a
Explanation: The NAND & NOR gates are known as universal gates because any digital circuit can be realized completely by using either of these two gates.

57. The gates required to build a half adder are
a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) Four NAND gates
Answer: c
Explanation: The gates required to build a half adder are EX-OR gate and AND gate.